To satisfy the demand for large scale digital integrated circuits, the semiconductor industry has developed three basic approaches. These include standard, off the shelf circuits, custom circuits, and semicustom circuits. The standard, off the shelf circuit provides the lowest cost option due to the quantities manufactured, but are limited in providing the flexibility for the circuit desired. The custom circuit requires a long design cycle and is cost limiting unless the number of circuits desired is large. The semicustom circuit includes both standard cell and gate array chips. The semicustom approach provides a shorter design cycle time and lower engineering costs, but also has lower performance and transistor densities than the custom designs.
The gate array involves a standard array of a large number of predefined transistors diffused into a chip. The building block of the array is the core cell which typically includes two, four, or eight transistors arranged for maximum connectivity for forming many circuit functions. These core cells are then arranged in a plurality of rows and columns to form the array. In addition to the array, the periphery of the gate array is defined by input/output cells wherein the transistors are also predefined. A macro cell library is also designed which defines the metallization patterns necessary to interconnect the transistors within one or more core cells to form basic logic functions such as inverters, Nand and Nor gates, flip-flops, input and output cells, etc. A customer defines a design for the gate array by using macros from the macro cell library and specifying their interconnection to form the desired system functions.
The advantage of the gate array approach is in its low cost and short cycle time. And with product lifetimes decreasing there is tremendous pressure to reduce design and manufacturing times. The cost savings come from reduced engineering requirements and fewer custom mask sets required. This is because many wafers are processed up to the transistor level and then stored until they are needed for a customers design. In this way all customers share the cost of the masks required to process up to the transistor level in which case the cost becomes negligible. And since the transistors are predefined, it is not necessary to custom design and layout each of thousands of transistors. Time is saved both in design time and manufacturing since less engineering is required and the majority of the processing has been completed before a design is undertaken.
There are several disadvantages associated with the gate array design approach including lower transistor density due to inefficient transistor layout and many unused transistors which results in a larger chip, and lower performance. The cost per chip is higher, but for low volumes this is offset by the much lower engineering costs. As gate arrays evolve into larger die with more transistors it becomes possible to realize more complex systems on chip. This increases the need for more specialized macros with greater efficiency (i.e. less unused transistors). A specific problem is that of supplying memory efficiently on the gate array.
In providing Static Random Access Memory (SRAM) two options are available: providing a dedicated memory block on the chip, therein providing improved density and performance at a cost of flexibility; or providing a SRAM cell in the macro cell library which is flexible but inefficient (i.e., in a four transistor core cell, two core cells are required to implement a six transistor SRAM and thus wastes 2 transistors or 25 percent of the area). The same options and problems exist for providing Read Only Memory (ROM) on the gate array except that the problem is exacerbated by the fact that only P or N-channel transistors could be used in the ROM array, thus wasting 50 percent of the transistors in the core cells implementing the ROM array.
Thus, what is needed is a gate array macro cell having improved efficiency wherein a single SRAM bit is combined with two ROM bits to utilize all prediffused transistors in the core cell.